In the conventional method of manufacturing a multilayer circuit board, several double-sided boards are laminated together with intervening layers of dielectric material. Each double-sided board comprises a core layer of epoxy-glass having copper foils laminated to its two opposite sides. The copper foils that will not be exposed at the exterior of the multilayer circuit board are patterned and selectively etched to define respective inner layers of conductor runs. The patterns are defined with reference to alignment holes that are drilled in the border area of the board. After etching of the inner layers, alignment pins are fitted through the alignment holes in each board to form a "book", there being a sheet of glass-reinforced epoxy material interposed between each two adjacent double-sided boards in the book, and the boards are laminated together under heat and pressure. In order to form interconnections between conductor runs that are in different layers, holes are drilled through the laminated assembly, exposing at the interior of the holes the conductor runs that are penetrated by the holes. The assembly is then electrolessly plated with copper, and copper deposited inside the holes interconnects the conductor runs that are penetrated by the holes and also connects those conductor runs to the outer (as yet unitary) copper foils. The outer foils are then masked and selectively etched to form outer layers of conductor runs.
There are numerous practical difficulties associated with this conventional method. First, the drill bit that is used to drill the holes through the laminated assembly must be sufficiently thick to be strong enough to penetrate the assembly, and this implies that in order to have a cost-effective production run the drill bits must be at least 13 to 20 mils (1 mil is 0.001 inch, or about 0.025 mm) in diameter. The lands of the inner conductor runs that are penetrated by the drill bit must be at least about 25 to 30 mils across in order to be sure that they will be penetrated, and conductor runs that are not to be penetrated must be at least about 25 to 30 mils from the nominal center of the hole in order to be sure that connections will not inadvertently be made to those conductor runs. The method used for aligning the patterns of conductor runs on the several double-sided boards that make up the multilayer board implies a possible error of as much as 5 mils in alignment of lands in different conductor run layers. Therefore, although commercially-available NC drilling machines are able to position a drill bit to within 1 mil of a desired position, other constraints make it impossible to take advantage of this capability, and in any event the size of the lands of circuit runs that are interconnected through drilled holes places a lower limit on the separation of the features of a circuit board manufactured by the conventional method.
In U.S. Pat. No. 4,211,603, two methods of manufacturing a multilayer circuit board are described. In accordance with the first method, the starting material is a double-sided circuit board having a core and two inner layers of conductor runs on the opposite face respectively of the core. Conductor runs of the two inner layers are selectively interconnected by plated through-holes in the board. The conductor run layers are covered with respective layers of dielectric material, while leaving the through-holes open and the plated interiors of the through-holes exposed. The board is then plated with a continuous layer of metal, and films of photoresist are applied over the two opposite faces of the board, covering the throughholes. The photoresist layers are selectively exposed and the unexposed areas of photoresist are removed, and the thus-exposed metal of the plated layer is removed by chemical etching. The remaining portions of the photoresist are then stripped from the board, leaving outer conductor run layers that are selectively interconnected through the plated through-holes.
In the second method described in the U.S. Pat. No. 4,211,603 the starting material is the same. Layers of dielectric material are screened onto the opposite sides of the board, overlying the inner conductor run layers but leaving selected portions of those layers, including the pads surrounding the through-holes, exposed. A continuous layer of copper is plated on the board, completely covering the screened layers of dielectric material, the exposed portions of the conductor run layers and the plated interiors of the through-holes. Films of dry photoresist are laminated to the opposite sides of the board and are exposed and developed, and the thus-exposed areas of the continuous layer of copper are removed. The exposed photoresist material is then stripped from the board. The portions of the continuous layer of copper that remain form outer conductor run layers that are connected to the inner conductor run layers at locations of the inner layers that were left exposed by the screened dielectric material. The methods described in U.S. Pat. No. 4,211,603 are not applicable to use with surface mount technology, because of the relatively poor adhesion of electrolessly-deposited copper to the screened dielectric material. Moreover, it is not normally possible to position the screen to better than 10 mils, and it is not possible to use screening to define features that are smaller than 20 mils, and therefore these methods are not applicable to high density, high precision circuit boards.
It has previously been proposed that a laser light source should be used to form vias in printed circuit boards. However, this proposal has not reached commercial application because the energy needed to vaporize the dielectric material, i. e. epoxy glass, is so variable that it has not been possible to produce reliable, clean and smooth vias.